/dts-v1/; /plugin/; / { compatible="brcm,bcm2708"; fragment@0 { target = <&spi0>; __overlay__ { status = "okay"; spidev@0 { status = "disabled"; }; spidev@1 { status = "disabled"; }; }; }; fragment@1 { target = <&spi0>; __overlay__ { /* needed to avoid dtc warning */ #address-cells = <1>; #size-cells = <0>; ice40: ice40@0 { compatible = "lattice,ice40-fpga-mgr"; reg = <0>; spi-max-frequency = <10000000>; cdone-gpios = <&gpio 24 0>; reset-gpios = <&gpio 22 1>; }; }; }; };
outdir=_out/ src= synthesize: $(outdir)counter.bin $(outdir)counter.bin: counter.v counter.pcf $(src) mkdir -p $(outdir) yosys -q -p "synth_ice40 -blif $(outdir)counter.blif" counter.v $(src) arachne-pnr -d 8k -p counter.pcf $(outdir)counter.blif -o $(outdir)counter.txt icepack $(outdir)counter.txt $(outdir)counter.bin .PHONY: synthesize
module top(input ref_12mhz, output test1, output test2, output [7:0] leds); reg [23:0] counter = 0; always @(posedge ref_12mhz) counter <= counter + 1; assign leds[0:7] = counter[16:23]; assign test1 = counter[4]; assign test2 = !counter[4]; endmodule
set_io ref_12mhz J3 set_io test1 M1 set_io test2 M2 set_io leds[0] B5 set_io leds[1] B4 set_io leds[2] A2 set_io leds[3] A1 set_io leds[4] C5 set_io leds[5] C4 set_io leds[6] B3 set_io leds[7] C3